The protection of surfaces or structures fabricated on a semiconductor substrate from radiation employed during fabrication have been a common practice throughout semiconductor technology. That is, during proton implantation and other radiation procedures employed in the manufacture of semiconductor devices, scattered beta, proton, x-ray and gamma particles can damage previously formed semiconductor devices. For example, the scattered particles can introduce defects in the crystalline lattice of doped regions of the devices, and can also cause charge build-up in the doped regions and the gate components. A high flux of ionizing radiation can also induce positive charge in various dielectric regions of a semiconductor device, thereby inducing parasitic transistors which conduct when actual operating transistors are not conducting. Consequently, semiconductor device components and surfaces may be protected by employing one or more photo-sensitive layers, oxides or other hard mask layers, and/or by introducing impurities into one or more features, thereby electrically isolating one region from scattered radiation while other regions on a semiconductor substrate are intentionally irradiated.
One common protection scheme includes fabricating a region of electrical isolation or protection by the impingement of ionizing radiation. Patterned portions of a semiconductor device may be exposed to an ionizing radiation source such as an ion or proton beam. The open patterned areas can be implanted with an impurity to create defect interstitials that change the electrical properties of an open patterned semiconductor device. During the radiation process, ionizing radiation scatters throughout the microelectronics device such that some un-targeted regions of the microelectronics device are exposed to the ionizing radiation. The scattered radiation can irrevocably damage the microelectronics device.
Another technique to minimize or reduce the effect of scattered ionizing radiation is to increase the distance between the targeted region from the un-targeted region. However, the increased distance or spacing reduces the overall area of the semiconductor substrate and reduces the allowable device area density. Moreover, such protection schemes become increasingly challenging as scaling continues to shrink device geometries.